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ADT7476
Example:
TACH1 High Byte (0x29) = 0x17
TACH1 Low Byte (0x28) = 0xFF
What is Fan 1 speed in RPM?
Fan startup timeout can be disabled by setting Bit 5
(FSPDIS) of Configuration Register 1 (0x40).
Table 39. PWM1 TO PWM3 CONFIGURATION
(REG. 0X5C TO 0X5E)
Fan 1 TACH Reading = 0x17FF = 6143 (decimal)
RPM = (f × 60)/Fan 1 TACH Reading
RPM = (90,000 × 60)/6143
Fan Speed = 879 RPM
TACH Pulses per Revolution
Different fan models can output either one, two, three, or
four TACH pulses per revolution. Once the number of fan
TACH pulses has been determined, it can be programmed
into the TACH Pulses per Revolution Register (0x7B) for
Bit
[2:0]
Mnemonic
SPIN
Description
These bits control the startup
timeout for PWM1 (0x5C),
PWM2 (0x5D), PWM3 (0x5E).
000 = No Startup Timeout
001 = 100 ms
010 = 250 ms (Default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
each fan. Alternatively, this register can be used to determine
the number of pulses per revolution output by a given fan.
By plotting fan speed measurements at 100% speed with
different pulses per revolution settings, the smoothest graph
with the lowest ripple determines the correct pulses per
revolution value.
Table 37. FAN PULSES/REVOLUTION REGISTER
Disabling Fan Startup Timeout
Although fan startup makes fan spin-ups much quieter
than fixed-time spin-ups, the option exists to use fixed
spin-up times. Setting Bit 5 (FSPDIS) to 1 in Configuration
Register 1 (0x40) disables the spin-up for two TACH pulses.
Instead, the fan spins up for the fixed time as selected in
Register 0x5C to Register 0x5E.
(REG. 0X7B)
Bit Mnemonic
Description
PWM Logic State
The PWM outputs can be programmed high for 100%
[1:0]
[3:2]
[5:4]
[7:6]
FAN1 Default
FAN2 Default
FAN3 Default
FAN4 Default
2 Pulses per Revolution
2 Pulses per Revolution
2 Pulses per Revolution
2 Pulses per Revolution
duty cycle (non-inverted) or low for 100% duty cycle
(inverted).
Table 40. PWM1 TO PWM3 CONFIGURATION
(REG. 0X5C TO 0X5E) BITS
Table 38. FAN PULSES/REVOLUTION REGISTER
BIT VALUES
Bit
[4]
Mnemonic
INV
Description
0 = logic high for 100% PWM duty cycle
Value
00
01
10
11
Description
1 Pulse per Revolution
2 Pulses per Revolution
3 Pulses per Revolution
4 Pulses per Revolution
1 = logic low for 100% PWM duty cycle
Low Frequency Mode PWM Drive Frequency
The PWM drive frequency can be adjusted for the
application. Register 0x5F to Register 0x61 configure the
PWM frequency for PWM1 to PWM3, respectively.
Fan Spin-up
The ADT7476 has a unique fan spin-up function. It spins
Table 41. PWM FREQUENCY REGISTERS
(REG. 0X5F TO 0X61)
the fan at 100% PWM duty cycle until two TACH pulses are
detected on the TACH input. Once two TACH pulses have
been detected, the PWM duty cycle goes to the expected
running value, for example, 33%. Fans have different
spin-up characteristics and take different times to overcome
inertia. The advantage of the ADT7476 is that it runs the fans
just fast enough to overcome inertia and is quieter on spin-up
than fans that are programmed to spin up for a given time.
Bit
[2:0]
Mnemonic
FREQ
Description
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (Default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
Fan Startup Timeout
To prevent the generation of false interrupts as a fan spins
up (because it is below running speed), the ADT7476
includes a fan startup timeout function. During this time, the
ADT7476 looks for two TACH pulses. If two TACH pulses
are not detected, an interrupt is generated.
High Frequency Mode PWM Drive
Setting Bit 3 of Register 0x5F, Register 0x60, and
Register 0x61 enables high frequency mode for Fan 1,
Fan 2, and Fan 3 respectively.
In high frequency mode, the PWM drive frequency is
always 22.5 kHz. When high frequency mode is enabled, the
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